I spent about five years working on compiler like tools for designing integrated circuits, first at Synopsys where I worked on the HDL Compiler for logic synthesis and then at Quickturn, where I was a project lead and one of the principle implementors of a hardware accelerated behavioral Verilog simulator.
The industry involved in creating software for chip design and simulation is refered to as the Electronic Design Automation (EDA) industry. This web page includes links to material from my days laboring in that particular vinyard.
This paper was written by Jerry Bauer, Mike Bershteyn and I. It describes work that Jerry, Mike, Paul Vyedin and I did. This paper was presented at the 1998 Design Automation Conference. The DAC reviewers tend to take a dim view of commercially oriented papers, so this paper provides a rather academic view of our work on the SimServer behavioral Verilog simulator. This simulator was designed to work with Quickturn's Mercury emulator. The Quickturn emulators are huge arrays of FPGAs (programmable logic). In addition to the FPGA array, the Mercury emulator included a set of powerPC microprocessors that could directly read and write to the FPGA array.
We built a compiler and runtime software that would allow behavioral Verilog to be compiled for simulation on the Mercury system. This would allow a Verilog behavioral test bench to be compiled along with a structural chip design. We hoped that this would provide a high performance simulation environment.
The Verilog compiler supported a very large subset of the Verilog language and generated both powerPC code and logic netlists.
A few small companies and some large EDA companies have proposed using languages like C or even C++ as hardware design langugages. This web page discusses why I believe that this approach is impractical. I give an example of the RSA Data Security RC5 cryptographic algorithm as an example. The C code, modified to show logical partitioning for hardware implementation is provided, along with RTL Verilog that implements the chip setup logic.
Just before the turn of the twenty-first century (that would be 1999) I designed and implemented a set of C++ objects for a VHDL compiler. The group I was working with had a VHDL front end and these data structures were designed for the intermediate that would be generated from processing the front end data structures. These objects were never used, so I'm publishing them here.
This Web page publishes a C++ program I wrote that generates cascade multipliers of an aribitrary width. A cascade multiplier is an array of adders that will perform an integer multiply in a single clock cycle. I wrote this to generate a test case for the SimServer system (and also because cascade multipliers have an interesting tiled, recursive structure).
ICCAD Seminar on Hardware/Software Codesign of Embedded Systems, November 9, 1995
This is a trip report from a seminar I attended on Hardware/Software Co-design. Hardware/Software Co-design refers to a so far mythical system that would allow a chip and its associated software environment to be designed together. The design system would allow the user to make trade-offs between what was implemented in hardware and what was implemented in software. Feedback would be provided on the performance and chip size implications of these design decisions. The system might include compiler development tools that would allow a compiler to be customized for the hardware. These are great ideas, but this is an area where there has been more heat than light.
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