This web page publishes a set of C++ objects developed for a VHDL compiler. I developed this software in early 1999, but it was never used in a product (it's a long story). This software consists of about 5K lines of source code and comments. This source code is free for non-commercial use. If you have a commercial appliction in mind, let me know and I'm sure that we can work out a reasonable license.
The VHDL compiler was the second hardware design language compiler my colleagues and I developed. The first compiler was for the Verilog hardware design language. The Verilog compiler, like the VHDL compiler we later developed, was targeted at the powerPC microprocessor. We started work on the VHDL compiler because, at the time, about half the designers used Verilog and half used VHDL. Without support for both languages you miss half of the market.
VHDL can be used to specify a hardware design (for implementation in a VLSI chip or in an FPGA). The process of compiling VHDL into the logic "netlist" that defines a hardware design is referred to as logic synthesis. VHDL can also be used to define the behavior of a hardware device or a system as well. For supporting behavioral models VHDL provides delays, events and processes. Behavioral VHDL is simulated, usually by compiling VHDL into an abstract instruction set (logically similar to Java byte code) or into machine code for a microprocessor.
VHDL is a complex language. VHDL is a modular language, like Ada and Modula-2. VHDL modules not only support name space modularization, as in Ada, but also hardware component definition. This allows a hardware component to be instantiated multiple times in a design.
To avoid the time consuming effort of developing a VHDL parser we purchased an existing VHDL compiler front end which did full VHDL parsing and validation (the front end did not, however, do elaboration, which is the process of instantiating the components of a VHDL design).
The VHDL front end generated a tree structured intermediate and a symbol table. Our plan was to convert this intermediate into our own abstract syntax trees, and later a control-flow/data-flow graph. From this graph we would generate a high level pseudo-instruction set intermediate that was used by or Verilog code generator. This would allow the VHDL and Verilog compilers to share the code generation phase.
The objects published here were designed to implement the tree structured intermediate. Once the new tree structured intermediate was generated, the front end data structures could be discarded. The objects published here include a symbol table suitable for VHDL and other supporting tables (a type table and a string table).
Each node in the abstract syntax tree (AST) has a type. Examples of node type include operators, like assignment and plus. A node may also have a leaf type, which would be a constant (an integer, for example) or an indentifier (a symbol). An identifier node will have a pointer to the symbol table entry for that identifier.
The abstract syntax tree (AST) is based on a polymorphic set of C++ types. The abstract base class is node. There are three concrete derived types:
Non-leaf nodes, like operators, are usually node_type nodes.
This AST node is used for VHDL constants. It contains a pointer to a polymorphic constant type.
This AST node is used for symbols. It contains a pointer into the symbol table for the associated symbol.
The process of compiling a complex language like VHDL involves transforming an abstract syntax tree into a simpler abstract syntax tree which can be processed by a later pass. Multiple compiler passes may sequentially transform the tree until the control flow/data flow graph is generated. The basic blocks in the control flow graph consisted of pseudo-instructions for a high level three address instruction set. Machine independent optimization is then performed on the graph. This includes local and global optimization. Then machine instructions are generated. Registers are assigned and local optimization is performed.
I wrote this code in 1999, about five years ago. While the code is not bad, there are definitely things that I would have done differently. For example, this code base includes a number of global enumerations. I would have made these enumerations local to a particular class. I also probably would have made the abstract base classes (node, sym and type) truely abstract, rather than providing virtual function implementations which asserted. And so on and so on...
This software has a definite C/C++ flavor. The C++ I write these days shows some influence from work I've done in Java. The data structures are designed to support compiling very large VHDL designs. The more memory efficient the data structures are, the larger the design that can be compiled. So some of these objects use C bit vectors, which has a somewhat archaic feel.
Finally this software is incomplete. A lot of the code is infrastructure support (templates for lists, fifos, a hash table). The basic C++ objects are filled out (support for the AST, types and symbols). There is a symbol table that supports VHDL scoping. To be honest, looking back I don't recall what I intended to do with the type table (after all, the names of types are stored in the symbol table). There is still work that would need to be done before a VHDL front end can be supported.
I don't know how useful this code will be to anyone but me. I really do make an effort to do a good job commenting my software. But looking back at this code I can see that the comments should have been much more complete (for example, what is the purpose of the type table?) A lot of work when into these objects, but the code that would use them is missing. Without this code the context of the application is not there, which makes it difficult to understand these objects.
The source code, as a gzip compressed, tar archive can be downloaded here [vhdl.tar.gz].
The Doxygen generated documentation can be found here
The code base include Makefiles for Windoz and Linux (pmake). On both Linux and Windoz (with the Microsoft Visual C++ 6.0 compiler) the code compiles and links.
Ian Kaplan, April 2004
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