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To work as a senior engineer or project lead on the design and development of large complex software systems. I have wide experience that includes quantitative financial modeling, trading systems, embedded systems, VLSI design tools, and extensive compiler development experience.
October 2002 to present, Staff Computer Scientist, Lawrence Livermore National Laboratories, Livermore CA
ADVISE Distributed Semantic Graph System Database System
August 2000 to July 2002, Senior Software Engineer, Prediction Company, Santa Fe, New Mexico
As part of a small team, worked on the design and implementation of a computerized equity trading system capable of supporting near real time orders submitted by multiple trading products. I wrote a large portion of the design documentation for this system, which evolved through three major design iterations. I implemented the XML parser front-end which provided the first stage for order and command processing.
Developed wavelet filter based predictors for financial modeling and trading. Applied a variety of statistical tests to verify the effectiveness of the wavelet predictors. These wavelet predictors were integrated into a test version of the Prediction Company US equity market predictor base. This work resulted in three research reports. This initial work on wavelets at Prediction Company sparked a strong interest in signal processing which I have continued to pursue (see my web pages on Wavelets and Signal Processing).
Maintained and extended Prediction Company's time series software and financial modeling infrastructure. This work included extension and support for an in-house data flow language for financial modeling. To make this software more accessible to Prediction Company users I wrote documentation for Prediction Company's custom time series query language.
Quickturn Design Systems, San Jose, CA
March 1998 to July 2000, Project Lead, HDL Simulation Compilers
Project lead of a group of three engineers responsible for the development and enhancement of Quickturn's SimServer Verilog and VHDL native compilers. Worked extensively with customers and marketing porting Verilog applications and benchmarks. Developed project schedules. Added code generation support for VHDL and enhanced Verilog code generation and runtime support.
February 1996 to March 1998, Senior Software Engineer
Developed a behavioral Verilog HDL compiler for hardware/software co-simulation on a reconfigurable computer system. I have been a key member of a small team that developed this compiler, which is now in alpha test. I wrote over thirty-five thousand lines of C and C++ code for the front, middle, back end of this compiler. I have also developed a large part of the compiler runtime.
June 1995 to February 1996, Synopsys, Mountain View, CA
As a member of the Synopsys HDL Compiler group, I added over 1200 lines of C source code to speed the generation of logic net lists from HDL parse trees. Fixed a number of critical bugs in the HDL synthesis compiler. Learned both Verilog and VHDL. Acted as a reviewer for DAC '96.
April 1994 to June 1995, Migration Software Systems, Ltd., San Jose, CA
Wrote an entirely new code generator for the Microsoft C/C++ front end, targeting a 32-bit Japanese RISC microprocessor. This code generator consists of over 12K lines of code and output object in Microsoft's COFF format. Ported the Microsoft debugger and the Microsoft profiler to the IBM Power PC, running Windows NT. Worked on optimization in the GNU C/C++ compiler for the HP-PA RISC architecture.
November 1993 to April 1994, Microtec Research Inc., Sunnyvale, CA
Designed and implemented a code generator for Hitachi's H8/300H 32-bit microprocessor. Designed and implemented backend optimizations for Microtec's AMD 29K compiler.
July 1988 to November 1993, MasPar Computer Corp., Sunnyvale, CA
Developed a compiler for a dialect of ANSI C, with extensions to support massive parallelism. My work on this compiler included the middle pass and code generation for the MIPS R4000 and MasPar's RISC based parallel instruction set.
Developed a Fortran 90 compiler for MasPar's massively parallel processor. As one of the first sixteen MasPar employees and the first member of the MasPar Compiler Group, I was instrumental in the development of this compiler. This work included the front end, the middle pass and code generation for VAX, MIPS R4000, and the MasPar instruction set. This compiler ran under DEC's version of Berkeley UNIX.
Implemented a variety of run time support routines, including software for math intrinsics and parallel I/O. Visited a major customer site to give a seminar on Fortran 90. Supported several customers doing work with MasPar beta test software.
March 1987 to July 1988, ESL Inc., Advanced Technology Lab., Sunnyvale, CA
Assistant Program Manager for software. Responsible for the design and implementation of the software for a heterogeneous parallel processor (named MOSAIC), funded by the Advanced Research Projects Agency (ARPA). The heart of MOSAIC was a high speed switch that connected a Sun 4, a CMU Warp parallel processor and an Encore Multimax.
Supervised another software engineer in the development of a debugger and implemented a microcode compiler, using UNIX's YACC parser generator. Other system software developed under my direction included a UNIX driver and several system utilities.
Responsible for software budgeting and scheduling.
Gave several presentations at customer sites.
DOD Secret level clearance.
July 1984 to March 1987, Loral Instrumentation, Data Flow Group, San Diego, CA
Defined the architecture of a data flow parallel processor for signal and data stream processing.
Lead software engineer in the development of the programming environment. This included the design of a large grain data flow language and the implementation of a compiler for this language.
Took part in the yearly project plan and worked closely with marketing on product literature.
June 1980 to July 1984, NCR Systems Engineering-Torrey Pines, San Diego, CA
A Semantic Graph Query Language by Ian Kaplan, Lawrence Livermore National Laboratory, October 17, 2006 UCRL-TR-255447 (PDF format)
Wavelets and Signal Processing. This is an extensive set of web pages on wavelets, wavelet applications and the Fourier transform. A large body of extensively documented Java and C++ source code implementing wavelet, Fourier transform and statistical algorithms is published on these web pages.
String Container Class and Reference Counted Objects. This is a set of C++ reference counted classes that supports a string class modeled after Rogue Wave's RWCString.
An Email Filter for UNIX/Linux Based Email. This is a rule based email filter, implemented in C++.
The ANTLR Parser Generator. This set of Web pages discusses why the ANTLR parser generator should be used and provides a set of examples showing how ANTLR grammars can be used to generate parsers. These Web pages have been cited as references on the main ANTLR web site
A Reconfigurable Logic Machine for Fast Event-Driven Simulation by Jerry Bauer, Michael Bershteyn, Ian Kaplan and Paul Vyedin, Proc. 35th ACM/IEEE Design Automation Conference, 1998
The Modula-2 Programming Language by Ian Kaplan and Mike Miller, Hayden Press, 1986.
The Data Flow Graph Language by Ian Kaplan. Presented at the Second Annual SIAM Conference on Parallel Processing for Scientific Computing, Nov. 1985.
A Large Grain Data Flow Architecture, by Ian Kaplan, Proc. of the Workshop on Future Directions in Computer Architecture and Software, May 5-7 1986.
Programming the Loral LDF 100 Dataflow Machine, by Ian Kaplan, ACM SIGPlan Notices, May 1987
The LDF 100: A Large Grain Dataflow Parallel Processor, by Ian Kaplan, ACM Computer Architecture News, June 1987
C++, Java, C, Verilog, VHDL, Fortran 90, Pascal, Modula-2, C*, Scheme (an MIT LISP dialect), Franz LISP and Lucid.
My domain, www.bearcave.com, publishes C++ and Java source code for applications ranging from networking to digital signal processing. This site also publishes web pages that discuss a variety issues, including VLSI design tools, software engineering and project management.