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To work as a senior engineer developing reliable, maintainable, large scale software systems.
October 2002 to present, Staff Computer Scientist, Lawrence Livermore National Laboratories, Livermore CA
Computer Network Mapping and Analysis
As a member of a small software group I developed multi-threaded C++ device control software.
Text data-mining and document triage
As part of a two person team I built a document search and triage system for very large document sets. This Java software processed Microsoft documents, PDF files, email and images. The document search and triage made use of the Solr faceted search system.
Graph Database System
June - August 2008, Intra-day Trading System
I designed and implemented an intra-day trading system for a start-up hedge fund. The trading system used the Interactive Brokers platform for order execution.
August 2000 to July 2002, Senior Software Engineer, Prediction Company, Santa Fe, New Mexico
As part of a small team, I worked on the design and implementation of a computer driven equity trading system capable of supporting near real time orders submitted by multiple trading products. I wrote a large portion of the design documentation for this system, which evolved through three major design iterations.
I developed wavelet filter based predictors for financial modeling and trading and applied a variety of statistical tests to verify the effectiveness of the wavelet predictors.
I maintained and extended Prediction Company's time series software and financial modeling infrastructure. I documented this system so it could be used by Prediction Company quantitative analysts.
Quickturn Design Systems, San Jose, CA
March 1998 to July 2000, Project Lead, HDL Simulation Compilers
As a project lead for a group of three engineers, I was responsible for the development and enhancement of Quickturn's SimServer Verilog and VHDL native compilers. I worked extensively with customers and marketing. I developed project schedules. In addition to my work as a project lead, I wrote the code generation phase for the VHDL compiler and enhanced Verilog code generation and runtime support.
February 1996 to March 1998, Senior Software Engineer
I developed a behavioral Verilog HDL compiler for hardware/software co-simulation on a reconfigurable computer system. As a key member of a small team that developed the Verilog compiler, I wrote over thirty-five thousand lines of C and C++ code for the front, middle, back end of this compiler. I also developed a large portion of the Verilog runtime.
June 1995 to February 1996, Synopsys, Mountain View, CA
As a member of the Synopsys HDL Compiler group, I added over 1200 lines of C source code to speed the generation of logic net lists from HDL parse trees.
April 1994 to June 1995, Migration Software Systems, Ltd., San Jose, CA
I wrote an entirely new code generator phase for the Microsoft C/C++ front end, targeting a Hitachi 32-bit RISC microprocessor. This code generator consists of over 12K lines of code. I ported the Microsoft debugger and the Microsoft profiler to the IBM Power PC, running Windows NT. I implemented a variety of code optimizations for the GNU C/C++ compiler for the HP-PA RISC architecture.
November 1993 to April 1994, Microtec Research Inc., Sunnyvale, CA
I designed and implemented a code generator for Hitachi's H8/300H 32-bit microprocessor and a variety of back-end optimizations for Microtec's AMD 29K compiler.
July 1988 to November 1993, MasPar Computer Corp., Sunnyvale, CA
As part of a small team I developed a compiler for a dialect of ANSI C, with extensions to support massive parallelism.
I developed a Fortran 90 compiler for MasPar's massively parallel processor. As one of the first sixteen MasPar employees and the first member of the MasPar Compiler Group, I was instrumental in the development of this compiler. This work included the front end, the middle pass and code generation phases.
I implemented a variety of run time support routines, including software for math intrinsics and parallel I/O.
March 1987 to July 1988, ESL Inc., Advanced Technology Lab., Sunnyvale, CA
As the Assistant Program Manager for software I was responsible for the design and implementation of the software for a heterogeneous parallel processor. This work was funded by the Defense Advanced Research Projects Agency (ARPA). I was responsible for software budgeting and scheduling and customer presentations.
July 1984 to March 1987, Loral Instrumentation, Data Flow Group, San Diego, CA
As the Lead software engineer in the development of a programming environment for a data flow parallel processor I worked architectural design for both hardware and software. This included the design of a large grain data flow language and the implementation of a compiler for this language.
The Modula-2 Programming Language by Ian Kaplan and Mike Miller, Hayden Press, 1986.
Value Factors Do Not Forecast Returns for S&P 500 Stocks, by Ian Kaplan
(March 10, 2014). Available at SSRN:
Additional material can be found on Topics in Quantitative Finance
Implementing Graph Pattern Queries on a Relational Database by Ian L. Kaplan, Ghaleb M. Abdulla, S Terry Brugger, Scott R. Kohn, Lawrence Livermore National Laboratory, January 8, 2008, LLNL-TR-400310 (PDF format)
A Semantic Graph Query Language by Ian Kaplan, Lawrence Livermore National Laboratory, October 17, 2006 UCRL-TR-255447 (PDF format)
A Reconfigurable Logic Machine for Fast Event-Driven Simulation by Jerry Bauer, Michael Bershteyn, Ian Kaplan and Paul Vyedin, Proc. 35th ACM/IEEE Design Automation Conference, 1998
The Data Flow Graph Language by Ian Kaplan. Presented at the Second Annual SIAM Conference on Parallel Processing for Scientific Computing, Nov. 1985.
A Large Grain Data Flow Architecture, by Ian Kaplan, Proc. of the Workshop on Future Directions in Computer Architecture and Software, May 5-7 1986.
Programming the Loral LDF 100 Dataflow Machine, by Ian Kaplan, ACM SIGPlan Notices, May 1987
The LDF 100: A Large Grain Dataflow Parallel Processor, by Ian Kaplan, ACM Computer Architecture News, June 1987
Wavelets and Signal Processing. This is an extensive set of web pages on wavelets, wavelet applications and the Fourier transform. A large body of extensively documented Java and C++ source code implementing wavelet, Fourier transform and statistical algorithms is published on these web pages.
String Container Class and Reference Counted Objects. This is a set of C++ reference counted classes that supports a string class modeled after Rogue Wave's RWCString.
An Email Filter for UNIX/Linux Based Email. This is a rule based email filter, implemented in C++.
The ANTLR Parser Generator. This set of Web pages discusses why the ANTLR parser generator should be used and provides a set of examples showing how ANTLR grammars can be used to generate parsers. These Web pages have been cited as references on the main ANTLR web site
Java, C++, the R Statistics language, Verilog, VHDL, Fortran 90, Scheme
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