For the last few years, Transmeta has claimed a market niche based on low power, high performance processors. Transmeta has always been long on hype and short on real innovation. With a new generation of asynchronous processors, the real real low power, high performance chips are starting to arrive. Transmeta is dead. They just don't know it yet. The success of these asynchronous designs suggests that the days of VLSI chip designs based on clock trees may be numbered as well.
Asynch chip design eases process shift, EE Times, February 13, 2003
This is one of those EE Times corporate puff pieces, penned by the VP of Product Development at Fulcrum Microsystems. Although this article is written to promote Fulcrum, it contains some good information about the advantages of asynchronous design, especially as it relates to the increasingly small device (transistor) sizes. Carver Mead and others at the California Institute of Technology have been researching asynchronous VLSI design for almost a decade. Presumably Fulcrum is somewhat of a CalTech spin-off.
It's Time for Clockless Chips, Claire Tristra, MIT Technology Review, October 2001
The Return of Asynchronous Logic by S.B. Furber, University of Manchester
A brief overview of clocked design, its limitations and the advantages of asynchronous logic design.
Computers without Clocks: Asynchronous chips improve computer performance by letting each circuit run as fast as it can by Ivan Sutherland and Jo Ebergen, Scientific American, August 2002
Designing Fast Asynchronous Circuits, Ivan Sutherland and Jon Lexau, December 19, 2000
This paper provides some insight into the sort of problems that asynchronous design tools, like those developed by Fulcrum, must solve. As device density increases low level device and wire issues become more important, so the extra complexity of this design style (compared to clocked designs) may not actually be an additional burden over what has to be done for clocked designs.
Asynchronous Design Methodologies: An Overview by Scott Hauck, Proceedings of the IEEE, Vol. 83, No. 1, Pgs 69-93, January 1995
Ian Kaplan, January 2003
Revised: